1. Technical Field
The present invention generally relates to a semiconductor integrated circuit such as an integrated circuit (IC) and a large-scale integration (LSI). More particularly, the invention relates to a semiconductor integrated circuit that operates at more than one power potential.
2. Related Art
In recent years, with a view to enhancing the operational speed of various electronic equipments as well as lowering the electric power consumption thereof, progress has been made in the degrees of high integration and low-voltage operation of semiconductor integrated circuits including ICs and LSIs used in those equipments. However, in view of device-specific properties, it is extremely difficult to lower the operational voltage of all semiconductor integrated circuits in a unified manner. Thus, there arise some cases where two or more integrated circuits operating at different supply potentials are interconnected.
In order to cope with such cases, semiconductor integrated circuits having an input circuit operating at a high supply potential and an internal circuit operating at a low supply potential are being developed. The input circuit of a semiconductor integrated circuit thus operating at two types of supply potentials will be described below in referencing FIGS. 9 to 11.
FIG. 9 is a circuit diagram showing a first input circuit of a related art semiconductor integrated circuit. The input circuit shown in FIG. 9 includes (1) an inverter 1 that inputs a signal from an external circuit via an input pad, to invert and output the input signal when a supply potential HVDD (e.g. 3.3 V) is fed and (2) an inverter 2 that inverts the output signal from the inverter 1 to output to an internal circuit, when a supply potential LVDD (e.g. 1.8 V) is fed.
In the above semiconductor integrated circuit, the supply potential HVDD is not fed in some cases even when the supply potential LVDD is fed. Reasons for such cases include reduction of power consumption when there is no need to input a signal from outside. Since, in such a case, the output from the inverter 1 is in a high-impedance state, an inconsistency may occur in the input level of the inverter 2, thereby causing a through current 12 to flow in the inverter 2. In order to prevent such a situation, a control signal (gate-enabling signal), being synchronized with the ON/OFF of the supply potential HVDD, is used.
Thus, the input circuit has (1) an inverter 3 that inverts the gate-enabling signal when the supply potential LVDD is fed and (2) an N-channel MOS transistor 4 that performs a switching operation when the inverted gate-enabling signal is imprinted on the gate. The transistor 4 fixes the input potential of the inverter 2 at a low level when the gate-enabling signal is low-level, that is, when the inverted gate-enabling signal is high-level.
FIG. 10 is a timing chart showing changes in the supply potential HVDD and the gate-enabling signal. As shown therein, the gate-enabling signal turns high-level when the supply potential HVDD is fed, whereas it turns low-level when the supply potential HVDD is no more fed. However, some difference occurs in the timing of the changes in the gate-enabling signal with respect to the ON/OFF timing of the supply potential HVDD, thereby generating a time TA, where the gate-enabling signal is low-level even though the supply potential HVDD is fed, and/or a time TB, where the gate-enabling signal is high-level even though the supply potential is not fed.
In the case of the input circuit shown in FIG. 9, a through current I1 may flow in the inverter 1 because the transistor 4 is ON during the time TA where the supply potential HVDD is fed and the gate-enabling signal is low-level. On the other hand, a through current I2 may flow in the inverter 2 because the input level of the inverter 2 becomes inconsistent during the time TB where the supply potential HVDD is not fed and the gate-enabling signal is high-level.
FIG. 11 is a circuit diagram showing a second input circuit of the related art semiconductor integrated circuit. The input circuit shown therein has (1) an inverter 1 that inputs a signal from an external circuit via an input pad, to invert and output the input signal when the supply potential HVDD (e.g. 3.3 V) is fed and (2) a NAND circuit 5 that sets up a logical multiplication of the output signal from the inverter 1 and the gate-enabling signal when the supply potential LVDD (e.g. 1.8 V) is fed, to invert and output the result to an internal circuit.
In the case of the input circuit shown in FIG. 11, output from the NAND circuit 5 is forcibly fixed at a high level during the time TA where the supply potential HVDD is fed and the gate-enabling signal is low-level. On the other hand, a through current I3 may flow in the NAND circuit 5 because the input level of the inverter 2 becomes inconsistent during the time TB where the supply potential HVDD is not fed and the gate-enabling signal is high-level.
As a related art having connection with the examples described above, JP-A-6-236693 discloses a device that protects an integrated circuit against any undesired or unexpected power-offs so that data will not be stored or erased randomly. The device includes a cutoff means that is serially connected between a voltage supply generating a programming/erasing voltage VPP and the feeding input of an integrated circuit corresponding to the voltage supply. The device further includes a means that makes the cutoff means active by being connected to the voltage supply that generates a normal supply voltage VCC. The cutoff means is made active when the value of the voltage VCC falls lower than a threshold value, in order to protect data from being rewritten or erased. However, JP-A-6-236693 discloses no information about preventing a through current that occurs in an input circuit when any of the supply potentials is turned ON/OFF.